5 Mar
2020
5 Mar
'20
11:57 p.m.
Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39330 )
Change subject: soc/intel/tigerlake: add PcieRpAspm and PchPmPciePllSsc ......................................................................
Patch Set 1:
My second upstream patch. I want to see that I have got it right with these two, before attempting to create more.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib3067811b36f45f44527c2c81be74abf2d40addf
Gerrit-Change-Number: 39330
Gerrit-PatchSet: 1
Gerrit-Owner: Jes Klinke jbk@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: caveh jalali caveh@chromium.org
Gerrit-Comment-Date: Thu, 05 Mar 2020 22:57:45 +0000
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