Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44897 )
Change subject: Revert "soc/amd/acpi: Move ACPI IVRS generation to coreboot" ......................................................................
Revert "soc/amd/acpi: Move ACPI IVRS generation to coreboot"
This reverts commit 1916f8969b10e27fe06b3e0eb1caae632bd947f6.
Reason for revert: This is currently causing hangs when kernel enables ACPI mode on zork devices. Until the issue is debugged and fixed, reverting this change.
BUG=b:166519072,b:155307433 BRANCH=zork TEST=Verified that morphius device boots fine with and without serial console enabled images.
Change-Id: Idee1c7e829282427ee80f7d7071793b000936810 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/acpi/acpi.c M src/include/acpi/acpi_ivrs.h M src/soc/amd/picasso/agesa_acpi.c 3 files changed, 4 insertions(+), 563 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44897/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 0b65459..7873c0f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1626,7 +1626,7 @@ case VFCT: /* ACPI 2.0/3.0/4.0: 1 */ return 1; case IVRS: - return IVRS_FORMAT_MIXED; + return IVRS_FORMAT_FIXED; case DBG2: return 0; case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index fe0aa40..de3bdea 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -42,7 +42,6 @@
/* Extended Feature Support */ #define IVINFO_EFR_SUPPORTED 0x01 -#define EFR_FEATURE_SUP (1 << 27)
/* IVHD Flags Field */ #define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ @@ -64,7 +63,6 @@ #define IOMMU_FEATURE_PN_BANKS_SHIFT 17 #define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 #define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ -#define IOMMU_FEATURE_GLX_SHIFT 3
#define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ #define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ @@ -72,9 +70,8 @@ #define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GT_SUP (1 << 2) /* Type 10h only */ -#define IOMMU_FEATURE_NX_SUP (1 << 1) /* Type 10h only */ -#define IOMMU_FEATURE_XT_SUP (1 << 0) +#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ +#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */
/* IVHD Device Entry Type Codes */ #define IVHD_DEV_4_BYTE_ALL 0x01 @@ -111,64 +108,6 @@ #define IVHD_UID_INT 0x01 #define IVHD_UID_STRING 0x02
-#define IOMMU_CAP_ID 0x0f - -/* MMIO Offset 0x30: IOMMU Extended Feature Register */ -#define MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT 0 -#define MMIO_EXT_FEATURE_PRE_F_SUP (0x1 << MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT) -#define MMIO_EXT_FEATURE_PPR_SUP_SHIFT 1 -#define MMIO_EXT_FEATURE_PPR_SUP (0x1 << MMIO_EXT_FEATURE_PPR_SUP_SHIFT) -#define MMIO_EXT_FEATURE_XT_SUP_SHIFT 2 -#define MMIO_EXT_FEATURE_XT_SUP (0x1 << MMIO_EXT_FEATURE_XT_SUP_SHIFT) -#define MMIO_EXT_FEATURE_NX_SUP_SHIFT 3 -#define MMIO_EXT_FEATURE_NX_SUP (0x1 << MMIO_EXT_FEATURE_NX_SUP_SHIFT) -#define MMIO_EXT_FEATURE_GT_SUP_SHIFT 4 -#define MMIO_EXT_FEATURE_GT_SUP (0x1 << MMIO_EXT_FEATURE_GT_SUP_SHIFT) -#define MMIO_EXT_FEATURE_IA_SUP_SHIFT 6 -#define MMIO_EXT_FEATURE_IA_SUP (0x1 << MMIO_EXT_FEATURE_IA_SUP_SHIFT) -#define MMIO_EXT_FEATURE_GA_SUP_SHIFT 7 -#define MMIO_EXT_FEATURE_GA_SUP (0x1 << MMIO_EXT_FEATURE_GA_SUP_SHIFT) -#define MMIO_EXT_FEATURE_HE_SUP_SHIFT 8 -#define MMIO_EXT_FEATURE_HE_SUP (0x1 << MMIO_EXT_FEATURE_HE_SUP_SHIFT) -#define MMIO_EXT_FEATURE_PC_SUP_SHIFT 9 -#define MMIO_EXT_FEATURE_PC_SUP (0x1 << MMIO_EXT_FEATURE_PC_SUP_SHIFT) -#define MMIO_EXT_FEATURE_HATS_SHIFT 10 -#define MMIO_EXT_FEATURE_HATS_MASK (0x3 << MMIO_EXT_FEATURE_HATS_SHIFT) -#define MMIO_EXT_FEATURE_GATS_SHIFT 12 -#define MMIO_EXT_FEATURE_GATS_MASK (0x3 << MMIO_EXT_FEATURE_GATS_SHIFT) -#define MMIO_EXT_FEATURE_GLX_SHIFT 14 -#define MMIO_EXT_FEATURE_GLX_SUP_MASK (0x3 << MMIO_EXT_FEATURE_GLX_SHIFT) -#define MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT 16 -#define MMIO_EXT_FEATURE_SMI_F_SUP_MASK (0x3 << MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT) -#define MMIO_EXT_FEATURE_SMI_FRC_SHIFT 18 -#define MMIO_EXT_FEATURE_SMI_FRC_MASK (0x7 << MMIO_EXT_FEATURE_SMI_FRC_SHIFT) -#define MMIO_EXT_FEATURE_GAM_SUP_SHIFT 21 -#define MMIO_EXT_FEATURE_GAM_SUP_MASK (0x7 << MMIO_EXT_FEATURE_GAM_SUP_SHIFT) -#define MMIO_EXT_FEATURE_PAS_MAX_SHIFT 32 -#define MMIO_EXT_FEATURE_PAS_MAX_MASK (0x1fULL << MMIO_EXT_FEATURE_PAS_MAX_SHIFT) - -/* MMIO Offset 0x18: IOMMU Control Register */ -#define MMIO_CTRL_IOMMU_EN (1 << 0) -#define MMIO_CTRL_HT_TUN_EN (1 << 1) -#define MMIO_CTRL_PASS_PW (1 << 8) -#define MMIO_CTRL_RES_PASS_PW (1 << 9) -#define MMIO_CTRL_COHERENT (1 << 10) -#define MMIO_CTRL_ISOC (1 << 11) - -/* MMIO Offset 0x4000: Counter Configuration Register */ -#define MMIO_CNT_CFG_N_CNT_BANKS_SHIFT 12 -#define MMIO_CNT_CFG_N_COUNTER_BANKS (0x3f << MMIO_CNT_CFG_N_CNT_BANKS_SHIFT) -#define MMIO_CNT_CFG_N_COUNTER_SHIFT 7 -#define MMIO_CNT_CFG_N_COUNTER (0xf << MMIO_CNT_CFG_N_COUNTER_SHIFT) - -/* Capability offset 0 */ -#define CAP_OFFSET_0_IOTLB_SP_SHIFT 24 -#define CAP_OFFSET_0_IOTLB_SP (1 << CAP_OFFSET_0_IOTLB_SP_SHIFT) - -/// Capability offset 10h -#define CAP_OFFSET_10_MSI_NUM_PPR_SHIFT 27 -#define CAP_OFFSET_10_MSI_NUM_PPR (0x1f << CAP_OFFSET_10_MSI_NUM_PPR_SHIFT) - /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ typedef struct ivrs_ivhd_generic { uint8_t type; @@ -186,24 +125,6 @@ uint8_t reserved2; } __packed ivrs_ivhd_alias_t;
-/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */ -typedef struct acpi_ivrs_ivhd_40 { - uint8_t type; - uint8_t flags; - uint16_t length; - uint16_t device_id; - uint16_t capability_offset; - uint32_t iommu_base_low; - uint32_t iommu_base_high; - uint16_t pci_segment_group; - uint16_t iommu_info; - uint32_t iommu_attributes; - uint32_t efr_reg_image_low; - uint32_t efr_reg_image_high; - uint32_t reserved[2]; - uint8_t entry[0]; -} __packed acpi_ivrs_ivhd40_t; - typedef struct ivrs_ivhd_extended { uint8_t type; uint16_t dev_id; @@ -220,14 +141,4 @@ uint8_t variety; } __packed ivrs_ivhd_special_t;
-typedef struct ivrs_ivhd_f0_entry { - uint8_t type; - uint16_t dev_id; - uint8_t dte_setting; - uint8_t hardware_id[8]; - uint8_t compatible_id[8]; - uint8_t uuid_format; - uint8_t uuid_length; -} __packed ivrs_ivhd_f0_entry_t; - #endif /* __ACPI_ACPI_IVRS_H__ */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index a651d6e..fb168a1 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <acpi/acpi_ivrs.h> #include <console/console.h> #include <fsp/util.h> #include <FspGuids.h> #include <soc/acpi.h> #include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <stdlib.h> -#include <arch/mmio.h>
struct amd_fsp_acpi_hob_info { uint32_t table_size_in_bytes; @@ -45,479 +39,15 @@ return current; }
-unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); - ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; - memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); - - ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; - ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ - ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); - ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; - current += sizeof(ivrs_ivhd_special_t); - - ivhd_ioapic = (ivrs_ivhd_special_t *)current; - memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); - - ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; - ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ - ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); - ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; - current += sizeof(ivrs_ivhd_special_t); - - return current; -} - -static unsigned long ivhd_describe_hpet(unsigned long current) -{ - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); - ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; - - ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; - ivhd_hpet->reserved = 0x0000; - ivhd_hpet->dte_setting = 0x00; - ivhd_hpet->handle = 0x00; - ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); - ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; - current += sizeof(ivrs_ivhd_special_t); - - return current; -} - -static unsigned long ivhd_describe_f0_device(unsigned long current, - uint16_t dev_id, uint8_t datasetting) -{ - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); - ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *) current; - - ivhd_f0->type = IVHD_DEV_VARIABLE; - ivhd_f0->dev_id = dev_id; - ivhd_f0->dte_setting = datasetting; - ivhd_f0->hardware_id[0] = 'A'; - ivhd_f0->hardware_id[1] = 'M'; - ivhd_f0->hardware_id[2] = 'D'; - ivhd_f0->hardware_id[3] = 'I'; - ivhd_f0->hardware_id[4] = '0'; - ivhd_f0->hardware_id[5] = '0'; - ivhd_f0->hardware_id[6] = '4'; - ivhd_f0->hardware_id[7] = '0'; - - memset(ivhd_f0->compatible_id, 0, sizeof(ivhd_f0->compatible_id)); - - ivhd_f0->uuid_format = 0; - ivhd_f0->uuid_length = 0; - - current += sizeof(ivrs_ivhd_f0_entry_t); - return current; -} - -static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, - uint16_t end_devid, uint8_t setting) -{ - /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ - current = ALIGN_UP(current, 4); - ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; - - /* Create the start range IVHD entry */ - ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; - ivhd_range->dev_id = start_devid; - ivhd_range->dte_setting = setting; - current += sizeof(ivrs_ivhd_generic_t); - - /* Create the end range IVHD entry */ - ivhd_range = (ivrs_ivhd_generic_t *)current; - ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; - ivhd_range->dev_id = end_devid; - ivhd_range->dte_setting = setting; - current += sizeof(ivrs_ivhd_generic_t); - - return current; -} - -static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, - unsigned long *current, uint8_t type, uint8_t data) -{ - if (type == IVHD_DEV_4_BYTE_SELECT) { - /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ - *current = ALIGN_UP(*current, 4); - ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; - - ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); - ivhd_entry->dte_setting = data; - *current += sizeof(ivrs_ivhd_generic_t); - } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - *current = ALIGN_UP(*current, 8); - ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; - - ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); - ivhd_entry->dte_setting = data; - ivhd_entry->reserved1 = 0; - ivhd_entry->reserved2 = 0; - ivhd_entry->source_dev_id = parent->path.pci.devfn | - (parent->bus->secondary << 8); - *current += sizeof(ivrs_ivhd_alias_t); - } - - return *current; -} - -static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, - unsigned long *current, uint16_t *ivhd_length) -{ - unsigned int header_type, is_pcie; - unsigned long current_backup; - - header_type = dev->hdr_type & 0x7f; - is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); - - if (((header_type == PCI_HEADER_TYPE_NORMAL) || - (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { - /* Device or Bridge is PCIe */ - current_backup = *current; - add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); - *ivhd_length += (*current - current_backup); - } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { - /* Device is legacy PCI or PCI-X */ - current_backup = *current; - add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); - *ivhd_length += (*current - current_backup); - } -} - -static void add_ivhd_device_entries(struct device *parent, struct device *dev, - unsigned int depth, int linknum, int8_t *root_level, - unsigned long *current, uint16_t *ivhd_length) -{ - struct device *sibling; - struct bus *link; - - if (!root_level) - return; - - if (dev->path.type == DEVICE_PATH_PCI) { - if ((dev->bus->secondary == 0x0) && - (dev->path.pci.devfn == 0x0)) - *root_level = depth; - - if ((*root_level != -1) && (dev->enabled)) { - if (depth != *root_level) - ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); - } - } - - for (link = dev->link_list; link; link = link->next) - for (sibling = link->children; sibling; sibling = - sibling->sibling) - add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, - current, ivhd_length); -} - -static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs) -{ - acpi_ivrs_ivhd40_t *ivhd_40; - unsigned long current_backup; - int8_t root_level; - - /* - * These devices should be already found by previous function. - * Do not perform NULL checks. - */ - struct device *nb_dev = pcidev_on_root(0, 0); - struct device *iommu_dev = pcidev_on_root(0, 2); - - memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); - ivhd_40 = (acpi_ivrs_ivhd40_t *)current; - - /* Enable EFR */ - ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; - /* For type 40h bits 6 and 7 are reserved */ - ivhd_40->flags = ivrs->ivhd.flags & 0x3f; - ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); - /* BDF <bus>:00.2 */ - ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); - ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); - ivhd_40->iommu_base_low = ivrs->ivhd.iommu_base_low; - ivhd_40->iommu_base_high = ivrs->ivhd.iommu_base_high; - ivhd_40->pci_segment_group = 0x0000; - ivhd_40->iommu_info = ivrs->ivhd.iommu_info; - /* For type 40h bits 31:28 and 12:0 are reserved */ - ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000; - - if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { - ivhd_40->efr_reg_image_low = read32((void *)ivhd_40->iommu_base_low + 0x30); - ivhd_40->efr_reg_image_high = read32((void *)ivhd_40->iommu_base_low + 0x34); - } - - current += sizeof(acpi_ivrs_ivhd40_t); - - /* Now repeat all the device entries from type 10h */ - current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); - ivhd_40->length += (current - current_backup); - root_level = -1; - add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, - ¤t, &ivhd_40->length); - - /* Describe HPET */ - current_backup = current; - current = ivhd_describe_hpet(current); - ivhd_40->length += (current - current_backup); - - /* Describe IOAPICs */ - current_backup = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivhd_40->length += (current - current_backup); - - /* Describe EMMC */ - current_backup = current; - current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), - IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); - ivhd_40->length += (current - current_backup); - - return current; -} - -static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs) -{ - acpi_ivrs_ivhd11_t *ivhd_11; - ivhd11_iommu_attr_t *ivhd11_attr_ptr; - unsigned long current_backup; - int8_t root_level; - - /* - * These devices should be already found by previous function. - * Do not perform NULL checks. - */ - struct device *nb_dev = pcidev_on_root(0, 0); - struct device *iommu_dev = pcidev_on_root(0, 2); - - /* - * In order to utilize all features, firmware should expose type 11h - * IVHD which supersedes the type 10h. - */ - memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); - ivhd_11 = (acpi_ivrs_ivhd11_t *)current; - - /* Enable EFR */ - ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; - /* For type 11h bits 6 and 7 are reserved */ - ivhd_11->flags = ivrs->ivhd.flags & 0x3f; - ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); - /* BDF <bus>:00.2 */ - ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); - ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); - ivhd_11->iommu_base_low = ivrs->ivhd.iommu_base_low; - ivhd_11->iommu_base_high = ivrs->ivhd.iommu_base_high; - ivhd_11->pci_segment_group = 0x0000; - ivhd_11->iommu_info = ivrs->ivhd.iommu_info; - ivhd11_attr_ptr = (ivhd11_iommu_attr_t *) &ivrs->ivhd.iommu_feature_info; - ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; - ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks; - ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; - - if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { - ivhd_11->efr_reg_image_low = read32((void *)ivhd_11->iommu_base_low + 0x30); - ivhd_11->efr_reg_image_high = read32((void *)ivhd_11->iommu_base_low + 0x34); - } - - current += sizeof(acpi_ivrs_ivhd11_t); - - /* Now repeat all the device entries from type 10h */ - current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); - ivhd_11->length += (current - current_backup); - root_level = -1; - add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, - ¤t, &ivhd_11->length); - - /* Describe HPET */ - current_backup = current; - current = ivhd_describe_hpet(current); - ivhd_11->length += (current - current_backup); - - /* Describe IOAPICs */ - current_backup = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivhd_11->length += (current - current_backup); - - return acpi_fill_ivrs40(current, ivrs); -} - -static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) -{ - unsigned long current_backup; - uint64_t mmio_x30_value; - uint64_t mmio_x18_value; - uint64_t mmio_x4000_value; - uint32_t cap_offset_0; - uint32_t cap_offset_10; - int8_t root_level; - - struct device *iommu_dev; - struct device *nb_dev; - - nb_dev = pcidev_on_root(0, 0); - if (!nb_dev) { - printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); - printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); - - return (unsigned long)ivrs; - } - - iommu_dev = pcidev_on_root(0, 2); - if (!iommu_dev) { - printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); - - return (unsigned long)ivrs; - } - - if (ivrs != NULL) { - ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; - ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); - - /* BDF <bus>:00.2 */ - ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); - ivrs->ivhd.capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); - ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; - ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); - - cap_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset); - cap_offset_10 = pci_read_config32(iommu_dev, - ivrs->ivhd.capability_offset + 0x10); - mmio_x18_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x18); - mmio_x30_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x30); - mmio_x4000_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x4000); - - ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ? - IVHD_FLAG_PPE_SUP : 0); - ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PRE_F_SUP) ? - IVHD_FLAG_PREF_SUP : 0); - ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_COHERENT) ? - IVHD_FLAG_COHERENT : 0); - ivrs->ivhd.flags |= ((cap_offset_0 & CAP_OFFSET_0_IOTLB_SP) ? - IVHD_FLAG_IOTLB_SUP : 0); - ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_ISOC) ? - IVHD_FLAG_ISOC : 0); - ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_RES_PASS_PW) ? - IVHD_FLAG_RES_PASS_PW : 0); - ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_PASS_PW) ? - IVHD_FLAG_PASS_PW : 0); - ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? - IVHD_FLAG_HT_TUN_EN : 0); - - ivrs->ivhd.pci_segment_group = 0x0000; - - ivrs->ivhd.iommu_info = pci_read_config16(iommu_dev, - ivrs->ivhd.capability_offset + 0x10) & 0x1F; - ivrs->ivhd.iommu_info |= (pci_read_config16(iommu_dev, - ivrs->ivhd.capability_offset + 0xC) & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT; - - ivrs->ivhd.iommu_feature_info = 0; - ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_HATS_MASK) - << (IOMMU_FEATURE_HATS_SHIFT - MMIO_EXT_FEATURE_HATS_SHIFT); - - ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_GATS_MASK) - << (IOMMU_FEATURE_GATS_SHIFT - MMIO_EXT_FEATURE_GATS_SHIFT); - - ivrs->ivhd.iommu_feature_info |= (cap_offset_10 & CAP_OFFSET_10_MSI_NUM_PPR) - >> (CAP_OFFSET_10_MSI_NUM_PPR_SHIFT - - IOMMU_FEATURE_MSI_NUM_PPR_SHIFT); - - ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & - MMIO_CNT_CFG_N_COUNTER_BANKS) - << (IOMMU_FEATURE_PN_BANKS_SHIFT - MMIO_CNT_CFG_N_CNT_BANKS_SHIFT); - - ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & MMIO_CNT_CFG_N_COUNTER) - << (IOMMU_FEATURE_PN_COUNTERS_SHIFT - MMIO_CNT_CFG_N_COUNTER_SHIFT); - ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & - MMIO_EXT_FEATURE_PAS_MAX_MASK) - >> (MMIO_EXT_FEATURE_PAS_MAX_SHIFT - IOMMU_FEATURE_PA_SMAX_SHIFT); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_HE_SUP) - ? IOMMU_FEATURE_HE_SUP : 0); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GA_SUP) - ? IOMMU_FEATURE_GA_SUP : 0); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_IA_SUP) - ? IOMMU_FEATURE_IA_SUP : 0); - ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & - MMIO_EXT_FEATURE_GLX_SUP_MASK) - >> (MMIO_EXT_FEATURE_GLX_SHIFT - IOMMU_FEATURE_GLX_SHIFT); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GT_SUP) - ? IOMMU_FEATURE_GT_SUP : 0); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_NX_SUP) - ? IOMMU_FEATURE_NX_SUP : 0); - ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_XT_SUP) - ? IOMMU_FEATURE_XT_SUP : 0); - - /* Enable EFR if supported */ - ivrs->iv_info = pci_read_config32(iommu_dev, - ivrs->ivhd.capability_offset + 0x10) & 0x007fffe0; - if (pci_read_config32(iommu_dev, - ivrs->ivhd.capability_offset) & EFR_FEATURE_SUP) - ivrs->iv_info |= IVINFO_EFR_SUPPORTED; - - } else { - printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); - - return (unsigned long)ivrs; - } - - /* - * Add all possible PCI devices on bus 0 that can generate transactions - * processed by IOMMU. Start with device 00:01.0 - */ - current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); - ivrs->ivhd.length += (current - current_backup); - root_level = -1; - add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, - ¤t, &ivrs->ivhd.length); - - /* Describe HPET */ - current_backup = current; - current = ivhd_describe_hpet(current); - ivrs->ivhd.length += (current - current_backup); - - /* Describe IOAPICs */ - current_backup = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivrs->ivhd.length += (current - current_backup); - - /* If EFR is not supported, IVHD type 11h is reserved */ - if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) - return current; - - return acpi_fill_ivrs11(current, ivrs); -} - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n");
current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); - - /* IVRS */ - current = ALIGN(current, 8); - ivrs = (acpi_ivrs_t *) current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current);
/* Add SRAT, MSCT, SLIT if needed in the future */