Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7240
-gerrit
commit cd335b596268863242241f5b6f6b9988b9e59713 Author: Martin Roth martin.roth@se-eng.com Date: Tue Oct 28 18:57:48 2014 -0600
minnowmax: Tell the FSP to set TSEG to 8MB
Minnowboard Max was broken by commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI because TSEG wasn't set to 8MB by the FSP. The default in the FSP is 1MB.
Change-Id: I2e671a6ca0240e931399920c62439c36133789aa Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/mainboard/intel/minnowmax/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 4e3833e..a0ac7ae 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"