Hello build bot (Jenkins), Patrick Georgi, Jes Klinke, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44359
to look at the new patch set (#3).
Change subject: mainboard/google/volteer: Enable long cr50 ready pulses ......................................................................
mainboard/google/volteer: Enable long cr50 ready pulses
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register.
Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke jbk@chromium.org Bug: b:154333137 --- M src/drivers/spi/tpm/tpm.c M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 4 files changed, 25 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44359/3