[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update TCSS PM flow

[John Zhao (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Divya Sasidharan, Utkarsh H Patel, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45014

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Update TCSS PM flow
......................................................................

soc/intel/tigerlake: Update TCSS PM flow

s0ix fails while USB4 device is connected and PCIe tunneling is up.
There is need to change PM flow along with TBT firmware update. This
change invokes D3CE and D3CX in DMA _PS0 when _OFF was not called
earlier.

BUG=b:158777291
TEST=Validated s0ix with USB4 device connected along with TBT firmware
QS variants TBT_TGL_B0_CHROME_Release_Image_Rev33 image.

Signed-off-by: John Zhao 
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
---
M src/soc/intel/tigerlake/acpi/tcss.asl
M src/soc/intel/tigerlake/acpi/tcss_dma.asl
M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
3 files changed, 37 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45014/3