Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian.
Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email )
Change subject: soc/intel/cmn/pmc: Add support for early power off ......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/86336/comment/6b0301bd_615419bb?usp... : PS4, Line 93:
When searching through the entire Coreboot project using grep, it appears that the convention is to […]
Acknowledged
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/86336/comment/b5b06a7f_8d083da8?usp... : PS4, Line 640: printk(BIOS_EMERG, "This platform doesn't know how to power off before ramstage,"
I believe that the "before ramstage" part is inaccurate. According to my earlier testing on Panther Lake, it also isn't working before FSP-S in ramstage. The exclamation point seems unnecessary. Could we use a message such as:
"This platform cannot be powered off until the silicon initialization is complete; entering an infinite loop."
Also, how does this code addresses the before FSP-S powering off in ramstage ?
This change addresses planned shutdowns on ChromeOS devices in specific scenarios, but does not circumvent underlying silicon poweroff limitations. Specifically:
- Early poweroff before FSP-M (for eSOL) is implemented using ChromeOS APIs. - Poweroff after FSP-S (for the low-battery logo) is already supported.
Poweroff failures prior to FSP-S indicate a silicon limitation and are not addressed by this change.