[coreboot-gerrit] Change in coreboot[master]: soc/skylake: add ACPI method to generate USB port info

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19975 )

Change subject: soc/skylake: add ACPI method to generate USB port info
......................................................................

soc/skylake: add ACPI method to generate USB port info

Add ACPI method GPLD to generate port location data when
passed visiblity info.  Will be used by _PLD method in
board-specific USB .asl files.

Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19975/1

diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 4c6625e..08f35bc 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -223,6 +223,26 @@
    {
    	Name (_ADR, Zero)

+		// GPLD: Generate Port Location Data (PLD)
+		Method (GPLD, 1, Serialized)
+		 {
+
+			Name (PCKG, Package (0x01)
+			{
+				Buffer (0x10) {}
+			})
+
+			// REV: Revision 0x02 for ACPI 5.0
+			CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+			Store (0x02, REV)
+
+			// VISI: Port visibility to user per port
+			CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+			Store (Arg0, VISI)
+
+			Return (PCKG)
+		}
+
    	/* USB2 */
    	Device (HS01) { Name (_ADR, 1) }
    	Device (HS02) { Name (_ADR, 2) }