[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: C-state IO base address aligment

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44135

to review the following change.

Change subject: mb/google/zork: C-state IO base address aligment
......................................................................

mb/google/zork: C-state IO base address aligment

Align the C-state MSR value of BSP with AGESA.

BUG=b:162705221
BRANCH=none
TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool

Signed-off-by: Chris Wang 
Change-Id: Ib98d34af518439d338326446c20601867ad31690
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/include/soc/iomap.h
2 files changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44135/1

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 526900a..039e3c2 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -257,6 +257,12 @@
    help
      Base address for the ACPI registers.

+config PICASSO_CSTATE_IO_BASE_ADDR
+	hex
+	default 0x413
+	help
+	  Base address for the CC6 State.
+
 config PICASSO_CONSOLE_UART
    bool "Use Picasso UART controller for console"
    default n
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 6b9ad2a..360b348 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -64,12 +64,12 @@
 /* I/O Ranges */
 #define ACPI_SMI_CTL_PORT		0xb2
 #define PICASSO_ACPI_IO_BASE	CONFIG_PICASSO_ACPI_IO_BASE
+#define  ACPI_CPU_CONTROL	CONFIG_PICASSO_CSTATE_IO_BASE_ADDR
 #define  ACPI_PM_EVT_BLK	(PICASSO_ACPI_IO_BASE + 0x00)     /* 4 bytes */
 #define  ACPI_PM1_STS		(ACPI_PM_EVT_BLK + 0x00)	  /* 2 bytes */
 #define  ACPI_PM1_EN		(ACPI_PM_EVT_BLK + 0x02)	  /* 2 bytes */
 #define  ACPI_PM1_CNT_BLK	(PICASSO_ACPI_IO_BASE + 0x04)     /* 2 bytes */
 #define  ACPI_PM_TMR_BLK	(PICASSO_ACPI_IO_BASE + 0x08)     /* 4 bytes */
-#define  ACPI_CPU_CONTROL	(PICASSO_ACPI_IO_BASE + 0x0c)     /* 6 bytes */
 /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */
 #define  ACPI_GPE0_BLK		(PICASSO_ACPI_IO_BASE + 0x20)     /* 8 bytes */
 #define  ACPI_GPE0_STS		(ACPI_GPE0_BLK + 0x00)		  /* 4 bytes */