Attention is currently required from: Martin Roth, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50928 )
Change subject: [WIP]security/intel/cbnt: Add options to generate BPM from Kconfig ......................................................................
Patch Set 14:
(4 comments)
File src/security/intel/cbnt/Kconfig:
https://review.coreboot.org/c/coreboot/+/50928/comment/3f17b4b1_8685919a PS14, Line 41: config INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE Looks like this belongs to the previous commit?
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/50928/comment/3794a980_8bc7312e PS14, Line 91: config INTEL_PCH_PWRM_BASE_ADDRESS I'd suggest making two separate patches to move these BARs from iomap.h to Kconfig
https://review.coreboot.org/c/coreboot/+/50928/comment/b4dff569_1b69aa34 PS14, Line 97: config INTEL_CBNT_CMOS_OFFSET This should be checked to ensure cmos.layout properly reserves this space. Should it be covered by checksum or not? Something like what I suggested in CB:51230 would be a good start.
That being said, I don't think any Xeon-SP boards use CMOS for coreboot options right now, but it could change.
https://review.coreboot.org/c/coreboot/+/50928/comment/944db315_e5f28e1e PS14, Line 101: CBNT style nit: `CBnT`