11 Apr
2020
11 Apr
'20
6:31 p.m.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40106 )
Change subject: soc/intel/tigerlake: Disable MrcSafeConfig ......................................................................
Patch Set 3:
Patch Set 1: Code-Review-1
Sounds like we will need to wait to merge this until the FSP uprev (b:150357377) occurs. Setting to -1 CR so that it doesn't merge prematurely.
Change is ready to be merged. All other pieces are ready. So going ahead and submitting this.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
Gerrit-Change-Number: 40106
Gerrit-PatchSet: 3
Gerrit-Owner: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
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