Marc Jones (marc@marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17140
-gerrit
commit 8c2fd0fb18d4483f8b6654d07612e8cd1db4bdfb Author: Marc Jones marcj303@gmail.com Date: Tue Sep 20 20:27:46 2016 -0600
cpu/amd: Update files for 00670F00
Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files.
Original-Signed-off-by: Marc Jones marcj303@gmail.com Original-Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Original-Tested-by: Marshall Dawson marshalldawson3rd@gmail.com (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7)
Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones marcj303@gmail.com --- src/cpu/amd/pi/00670F00/Kconfig | 6 ++-- src/cpu/amd/pi/00670F00/chip_name.c | 4 +-- src/cpu/amd/pi/00670F00/fixme.c | 50 ++++++++++++++++++--------------- src/cpu/amd/pi/00670F00/model_15_init.c | 20 ++++++------- src/cpu/amd/pi/Kconfig | 4 ++- src/cpu/amd/pi/Makefile.inc | 3 +- 6 files changed, 46 insertions(+), 41 deletions(-)
diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index de74d3c..d5e3abb 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. +# Copyright (C) 2015-2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -13,12 +13,12 @@ # GNU General Public License for more details. #
-config CPU_AMD_PI_00660F01 +config CPU_AMD_PI_00670F00 bool select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS
-if CPU_AMD_PI_00660F01 +if CPU_AMD_PI_00670F00
config CPU_ADDR_BITS int diff --git a/src/cpu/amd/pi/00670F00/chip_name.c b/src/cpu/amd/pi/00670F00/chip_name.c index ff2bc06..3ad62e5 100644 --- a/src/cpu/amd/pi/00670F00/chip_name.c +++ b/src/cpu/amd/pi/00670F00/chip_name.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,6 +15,6 @@
#include <device/device.h>
-struct chip_operations cpu_amd_pi_00660F01_ops = { +struct chip_operations cpu_amd_pi_00670F00_ops = { CHIP_NAME("AMD CPU Family 15h") }; diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 9a38bd8..f892af8 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -25,37 +25,39 @@ void amd_initcpuio(void) AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. + /* The platform BIOS needs to ensure the memory ranges of SB800 + * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and + * ACPI) are set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -68,27 +70,29 @@ void amd_initmmio(void) AMD_CONFIG_PARAMS StdHeader;
/* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. + Set the MMIO Configuration Base Address and Bus Range onto MMIO + configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ + (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + Set the NB_CFG MSR register. Enable CF8 extended config cycles. */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* For serial port */ PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ + 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); } diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index e252c3d..dd1c8e3 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,11 +41,11 @@ void PSPProgBar3Msr(void *Buffer) u32 Bar3Addr; u64 Tmp64; /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig (0x20); + Bar3Addr = PspLibPciReadPspConfig(0x20); Tmp64 = Bar3Addr; printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite (0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead (0xC00110A2, &Tmp64, NULL); + LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); }
static void model_15_init(device_t dev) @@ -59,7 +59,7 @@ static void model_15_init(device_t dev) u32 siblings; #endif
- disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -68,12 +68,12 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -89,9 +89,8 @@ static void model_15_init(device_t dev) /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - }
/* Enable the local CPU APICs */ @@ -130,8 +129,7 @@ static struct device_operations cpu_dev_ops = { };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, + { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, };
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 3e8d5c7..ed379ea 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00670F00 default y if CPU_AMD_PI_00660F01 default n select ARCH_BOOTBLOCK_X86_32 @@ -69,4 +70,5 @@ endif # CPU_AMD_PI
source src/cpu/amd/pi/00630F01/Kconfig source src/cpu/amd/pi/00730F01/Kconfig +source src/cpu/amd/pi/00670F00/Kconfig source src/cpu/amd/pi/00660F01/Kconfig diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 569c7af..0e31d9f 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,6 +15,7 @@
subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
romstage-y += s3_resume.c