[coreboot-gerrit] Change in coreboot[4.11_branch]: mb/fb/watson/watson_v2: configure PCI bifurcation

[Jonathan Zhang (Code Review)]

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41433 )

Change subject: mb/fb/watson/watson_v2: configure PCI bifurcation
......................................................................

mb/fb/watson/watson_v2: configure PCI bifurcation

Watson V2 server has different PCIe bifurcation configuration, comparing to
Watson server.

Add a watson_v2 variant directory. Allow variant to customize UPD parameters.

Configure UPD parameters to define PCIe bifurcation configuration for Watson
V2 server.

Change-Id: I3b57c64dea6f3a468336fcdb1e948dfcd897e60c
---
M src/mainboard/facebook/watson/Kconfig
M src/mainboard/facebook/watson/Makefile.inc
A src/mainboard/facebook/watson/include/variants.h
M src/mainboard/facebook/watson/romstage.c
A src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc
A src/mainboard/facebook/watson/variants/watson_v2/romstage.c
6 files changed, 61 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41433/1

diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig
index 009e8b5..f8f93df 100644
--- a/src/mainboard/facebook/watson/Kconfig
+++ b/src/mainboard/facebook/watson/Kconfig
@@ -41,6 +41,10 @@
    hex
    default 0x00800000

+config VARIANT_DIR
+	string
+	default "watson_v2" if BOARD_FACEBOOK_WATSON_V2
+
 config VBOOT_FWID_MODEL
    string
    default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)"
diff --git a/src/mainboard/facebook/watson/Makefile.inc b/src/mainboard/facebook/watson/Makefile.inc
index 1606476..f1384f7 100644
--- a/src/mainboard/facebook/watson/Makefile.inc
+++ b/src/mainboard/facebook/watson/Makefile.inc
@@ -14,3 +14,5 @@
 ##

ramstage-y += irqroute.c
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/facebook/watson/include/variants.h b/src/mainboard/facebook/watson/include/variants.h
new file mode 100644
index 0000000..0f1ed82
--- /dev/null
+++ b/src/mainboard/facebook/watson/include/variants.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/romstage.h>
+
+void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/facebook/watson/romstage.c b/src/mainboard/facebook/watson/romstage.c
index cf52c01..b8df798 100644
--- a/src/mainboard/facebook/watson/romstage.c
+++ b/src/mainboard/facebook/watson/romstage.c
@@ -17,6 +17,7 @@
 #include <stddef.h>
 #include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
+#include <variants.h>

/**
  * /brief mainboard call for setup that needs to be done before fsp init
@@ -41,5 +42,13 @@
  */
 void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 {
+	UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
+
+	/* Variant-specific memory params */
+	variant_romstage_fsp_init_params(UpdData);
+}
+
+__weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
+{

}
diff --git a/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc b/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc
new file mode 100644
index 0000000..29763fb
--- /dev/null
+++ b/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += romstage.c
diff --git a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c
new file mode 100644
index 0000000..4283fa0
--- /dev/null
+++ b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/romstage.h>
+#include <variants.h>
+
+void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
+{
+	/* Configure IOU1 as 4*4 lanes */
+	UpdData->ConfigIOU1_PciPort3 = 0;
+
+	/* Configure IOU2 as 2*4 lanes */
+	UpdData->ConfigIOU2_PciPort1 = 0;
+
+	/* Configure PCH PCIe ports as 8*1 lanes */
+	UpdData->PchPciPort1 = 1;
+	UpdData->PchPciPort2 = 1;
+	UpdData->PchPciPort3 = 1;
+	UpdData->PchPciPort4 = 1;
+	UpdData->PchPciPort5 = 1;
+	UpdData->PchPciPort6 = 1;
+	UpdData->PchPciPort7 = 1;
+	UpdData->PchPciPort8 = 1;
+
+	/* Enable hotplug for PCH PCIe ports */
+	UpdData->HotPlug_PchPciPort1 = 1;
+	UpdData->HotPlug_PchPciPort2 = 1;
+	UpdData->HotPlug_PchPciPort3 = 1;
+	UpdData->HotPlug_PchPciPort4 = 1;
+	UpdData->HotPlug_PchPciPort5 = 1;
+	UpdData->HotPlug_PchPciPort6 = 1;
+	UpdData->HotPlug_PchPciPort7 = 1;
+	UpdData->HotPlug_PchPciPort8 = 1;
+}