[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kangheui Won, Reka Norman, Paul Menzel, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov.

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/d2e502da_b94d2129 
PS1, Line 18:
> Creating a whole new CBMEM tag just for that is a bit annoying, it would be great if we could find a […]

The FSP reserved data contains the HOBs, among other things, so it should still be there in ramstage, it just needs to be extracted.

Patchset:

PS1:
> Hmm, that's a very good point, thanks. […]

I think you've made an excellent point about the complexity of this situation, and whether it is worth handling so many different flows. I think you've convinced me to go ahead and let's go with one flow (nissa flow). Please test it on ADL-P, ADL-N and TGL if possible.