Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36553 )
Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/c/coreboot/+/36553/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36553/4//COMMIT_MSG@12 PS4, Line 12: .
Sure i will
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 226: : Name (EP_B, 0) /* to store EP BAR */ : Name (MH_B, 0) /* to store MCH BAR */ : Name (PC_B, 0) /* to store PCIe BAR */ : Name (PC_L, 0) /* to store PCIe BAR Length */ : Name (DM_B, 0) /* to store DMI BAR
to avoid multiple read if any ? […]
let me take that AR to fix this soon from tgl
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 236: If (LEqual (MH_B, 0)) { : ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, MH_B) : }
use new syntax. Same applies to all files in this CL btw.
yes, planning to clean from TGL onwards
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 323: Store (_SB.PCI0.GMHB (), MBR0)
Are those functions necessary? Just do 'MBR0 = _SB.PCI0.MCHC. […]
will do with TGL changes
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 26: ^PCRA
use absolute references?
will do with TGL onwards