Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23679
Change subject: DRAFT: Normalize GPIO initialization on kahlee. ......................................................................
DRAFT: Normalize GPIO initialization on kahlee.
This makes the flow for GPIO initialization more closely folllow that for other boards.
Note: This will probably break gardenia so this can't go in as is, but I'm curious about comments on the strategy here.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest teravest@chromium.org --- M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/kahlee/bootblock/bootblock.c A src/mainboard/google/kahlee/ramstage.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/kahlee/gpio.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c A src/soc/amd/stoneyridge/include/soc/ramstage.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 11 files changed, 86 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23679/1
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 770a999..514373e 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -25,6 +25,7 @@ ramstage-y += chromeos.c ramstage-y += ec.c ramstage-y += OemCustomize.c +ramstage-y += ramstage.c
verstage-y += chromeos.c verstage-y += ec.c diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 90c8acb..244abe0 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -13,12 +13,18 @@ * GNU General Public License for more details. */
+#include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/southbridge.h> #include <variant/ec.h>
void bootblock_mainboard_init(void) { + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = variant_early_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); + /* Enable the EC as soon as we have visibility */ mainboard_ec_init();
diff --git a/src/mainboard/google/kahlee/ramstage.c b/src/mainboard/google/kahlee/ramstage.c new file mode 100644 index 0000000..7fdf495 --- /dev/null +++ b/src/mainboard/google/kahlee/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/ramstage.h> +#include <soc/southbridge.h> + +void ramstage_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = variant_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); +} + diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index a6bcea5..8d90174 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -258,13 +258,14 @@ { GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, };
-const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio - *board_get_gpio(size_t *size) +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { - if (GPIO_TABLE_BOOTBLOCK) { - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; - } + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +{ *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index bf14ef4..5bbc11d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -26,5 +26,7 @@ int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);
#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index e357c7e..d1cc017 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -96,12 +96,14 @@ {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, };
-const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { - if (GPIO_TABLE_BOOTBLOCK) { - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; - } + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +{ *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 709b413..3eff5eb 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -125,8 +125,6 @@ post_code(0x37); do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");
- sb_program_gpio(); - post_code(0x38); /* APs will not exit amdinitearly */ do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index d3a8bc4..bd48c74 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -24,6 +24,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/ramstage.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <amdblocks/agesawrapper.h> @@ -89,9 +90,16 @@ dev->ops = &stoneyridge_i2c_mmio_ops; }
+/* Mainboard GPIO configuration */ +__attribute__((weak)) void ramstage_mainboard_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + static void soc_init(void *chip_info) { southbridge_init(chip_info); + ramstage_mainboard_init(); setup_bsp_ramtop(); }
diff --git a/src/soc/amd/stoneyridge/include/soc/ramstage.h b/src/soc/amd/stoneyridge/include/soc/ramstage.h new file mode 100644 index 0000000..014c48b --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/ramstage.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +void ramstage_mainboard_init(void); + +#endif diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f4d6b17..259e8b5 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -350,9 +350,13 @@ /** * @brief program a particular set of GPIO * + * @param gpio_ptr = pointer to array of gpio configurations + * @param size = number of entries in array + * * @return none */ -void sb_program_gpio(void); +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size); /** * @brief Find the size of a particular wide IO * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 735642f..a14213f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -155,15 +155,13 @@ return irq_association; }
-void sb_program_gpio(void) +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size) { void *tmp_ptr; - const struct soc_amd_stoneyridge_gpio *gpio_ptr; - size_t size; uint8_t control, mux, index;
printk(BIOS_SPEW, "GPIO programming stage %s\n", STR_GPIO_STAGE); - gpio_ptr = board_get_gpio(&size); for (index = 0; index < size; index++) { mux = gpio_ptr[index].function; control = gpio_ptr[index].control; @@ -181,14 +179,6 @@ printk(BIOS_SPEW, "End GPIO programming\n"); }
-static void sb_program_gpio_ram(void *unused) -{ - sb_program_gpio(); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - sb_program_gpio_ram, NULL); - /** * @brief Find the size of a particular wide IO *