Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53924 )
Change subject: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition ......................................................................
doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Paul Menzel paulepanter@mailbox.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index e383c2e..6b629f4 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -52,4 +52,13 @@ Significant changes -------------------
+### AMD SoC cleanup and initial Cezanne APU support + +There's initial support for the AMD Cezanne APUs in the tree. This code +hasn't started as a copy of the previous generation, but was based on a +slightly modified version of the example/min86 SoC. During the cleanup +of the existing Picasso SoC code the common parts of the code were +moved to the common AMD SoC code, so that they could be used by the +Cezanne code instead of adding another slightly different copy. + ### Add significant changes here