[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Drop never-set DdrFreqLimit dt setting

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48574 )

Change subject: soc/intel/skylake: Drop never-set DdrFreqLimit dt setting
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soc/intel/skylake: Drop never-set DdrFreqLimit dt setting

Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.

Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/romstage/romstage.c
2 files changed, 1 insertion(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Michael Niewöhner: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4184233..67739a4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -93,12 +93,6 @@
    /* Whether to ignore VT-d support of the SKU */
    int ignore_vtd;

-	/*
-	 * DDR Frequency Limit
-	 * 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
-	 */
-	u16 DdrFreqLimit;
-
    /* Probeless Trace function */
    u8 ProbelessTrace;

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index a7ce2f8..79fb464 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -221,7 +221,7 @@
    m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
    m_cfg->RMT = config->Rmt;
    m_cfg->CmdTriStateDis = config->CmdTriStateDis;
-	m_cfg->DdrFreqLimit = config->DdrFreqLimit;
+	m_cfg->DdrFreqLimit = 0;
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
    m_cfg->PrmrrSize = get_valid_prmrr_size();
    for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {