[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/cmn: Clear interrupt status after HECI-1 has been received

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Johnny Lin, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Shuming Chu (Shuming), Shelly Chang.

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 )

Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
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Patch Set 4: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/66579/comment/b5d5c56a_b65b80a5 
PS4, Line 15:  get_me_fw_version
> My test result: […]

Thanks Lin for test results, it is clear the code clears the interrupt too early in your platform. Since coreboot code works in poll mode and communication between Host & CSE is request/response model, and clearing interrupt status again, I don't see any side effects. The change seems to be fine to me.