Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47505 )
Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob ......................................................................
vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
This field from SystemMemoryMapHob can be used to define error correction type in SMBIOS type 16.
Tested=On OCP Delta Lake, the value is expected.
Signed-off-by: Tim Chu Tim.Chu@quantatw.com Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index dc870f1..9f37459 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -143,21 +143,23 @@ UINT8 reserved2[22];
UINT8 DdrVoltage; - UINT8 reserved3[38]; + UINT8 reserved3[33]; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 reserved4[4]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved4[2213]; + UINT8 reserved5[2213]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved5[1603]; + UINT8 reserved6[1603];
UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
- UINT8 reserved6[24]; + UINT8 reserved7[24];
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 reserved7[5]; + UINT8 reserved8[5];
} SYSTEM_MEMORY_MAP_HOB;