Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ......................................................................
Patch Set 10:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... File src/mainboard/acer/es1-572/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... PS10, Line 3: PWRB No, PWRB isn't needed.
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... File src/mainboard/acer/es1-572/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... PS10, Line 1: only Um?
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... File src/mainboard/acer/es1-572/gpio.c:
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... PS10, Line 191: void mainboard_configure_gpios(void) This means GPIOs are programmed after FSP now?
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... File src/mainboard/acer/es1-572/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-572... PS10, Line 6: /* Name format: <pad name> / <net/pin name in schematics> */ : static const struct pad_config early_gpio_table[] = { : PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD / UART_2_CRXD_DTXD */ : PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD / UART_2_CTXD_DRXD */ : }; Are you sure this is required?