Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39473 )
Change subject: [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1 ......................................................................
[Hack] [TEST] Very Crude way of enabling IMGCLKOUT1
Signed-off-by: Pandya, Varshit B varshit.b.pandya@intel.com Change-Id: I5d0c99211b6ba43a1032322214058db688337b67 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl M src/soc/intel/tigerlake/finalize.c 2 files changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39473/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl index 8df60a8..f8c6ae0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -20,7 +20,7 @@ { Method (_ON, 0, Serialized) // _ON_: Power On { - MCCT(1,1,1) // Clock 0, enable, 19.2MHz + //MCCT(1,1,1) // Clock 0, enable, 19.2MHz //Check if another sensor is ON IF(STA0) { @@ -55,7 +55,7 @@ IF(STA0) { //Do nothing since the other sensor is ON - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } ELSE { @@ -63,7 +63,7 @@ CTXS(GPP_D13) //Disable PP2800 lane CTXS(GPP_D14) - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } Store(0,STA1) } diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index aed5cc0..fd5655d 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -108,6 +108,11 @@ pch_finalize();
printk(BIOS_DEBUG, "Finalizing SMM.\n"); + //Hack for enabling CLK + uint32_t test; + write32((void *)0xfdad800c, 0x2); + write32((void *)0xfdad800c, 0x3); + outb(APM_CNT_FINALIZE, APM_CNT);
/* Indicate finalize step with post code */