Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31498
Change subject: sb/intel/bd82x6x: Fix default IRQ mapping ......................................................................
sb/intel/bd82x6x: Fix default IRQ mapping
The default mapping was probably copy-pasted from a random board and disabled some interrupts (by implicitly clearing some register bits).
We provide a new default mapping with some reasoning, that tries to be most compatible (i.e. avoids to use PIRQ E-H that are not shareable on some boards).
Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362 Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/southbridge/intel/bd82x6x/early_rcba.c 1 file changed, 60 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31498/1
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 443b6c2..0dd7a56 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -23,40 +23,73 @@ southbridge_configure_default_intmap(void) { /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP SLOT1 INTA -> PIRQB - * D28IP_P2IP SLOT2 INTB -> PIRQF - * D28IP_P3IP SLOT3 INTC -> PIRQD - * D28IP_P5IP SLOT5 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - + * For the PCH internal PCI functions, provide a reasonable + * default IRQ mapping that utilizes only PIRQ A to D. Higher + * PIRQs are sometimes used for other on-board chips that + * require an edge triggered interrupt which is not shareable. */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + /* + * We use a linear mapping for the pin numbers. They are not + * physical pins, and thus, have no relation between the dif- + * ferent devices. Only rule we must obey is that a single- + * function device has to use pin A. + */ + RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); + RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | + (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | + (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(D22IP) = (INTA << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
- /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + /* + * For the PIRQ allocation the following was taken into + * account: + * o Interrupts of the PCIe root ports are only about + * events at the ports, not downstream devices. So we + * don't expect many interrupts there and ignore them. + * o We don't expect to talk constantly to the ME either + * so ignore that, too. Same for SMBus and the thermal + * device. + * o Second SATA interface is only used in non-AHCI mode + * so unlikely to coexist with modern interfaces (e.g. + * xHCI). + * o An OS that knows USB3 will likely also know how to + * use MSI. + * + * The functions that might matter first: + * + * D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode) + * D31IP_SIP2 SATA 2 -> PIRQ B + * D29IP_E1P EHCI 1 -> PIRQ C + * D27IP_ZIP HDA -> PIRQ D (MSI capable) + * D26IP_E2P EHCI 2 -> PIRQ D + * D25IP_LIP GbE -> PIRQ B (MSI capable) + * D20IP_XHCIIP xHCI -> PIRQ B (MSI capable) + * + * D31IP_TTIP Thermal -> PIRQ B + * D31IP_SMIP SMBUS -> PIRQ A + * D28IP_* PCIe RP -> PIRQ A-D (MSI capable) + * D22IP_MEI1IP ME -> PIRQ A (MSI capable) + * + * Note, CPU-integrated functions seem to always use PIRQ A. + */ +#define _none 0 + DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB); + DIR_ROUTE(D29IR, PIRQC, _none, _none, _none); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D26IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D25IR, PIRQB, _none, _none, _none); + DIR_ROUTE(D22IR, PIRQA, _none, _none, _none); + DIR_ROUTE(D20IR, PIRQB, _none, _none, _none); +#undef _none
/* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100;