Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35088 )
Change subject: soc/intel: always use pcidev_path_on_root_debug() ......................................................................
Patch Set 2: Code-Review-1
Patch Set 2: Code-Review-2
The trouble is the entire PCI subsystem in ramstage is based on matching the vendor/device ID register with a PCI driver and to the source we want to control that device with. To allow this hiding of PCI devices will ultimately force us to write the control somewhere in the scope of SOC instead. Oh, but wait, perhaps the intention is for us to __not__ write that control anymore but let the FSP blob do all that too!
AFAICS, hardware that does not respond to vendor/device ID register reads does not meet PCI compliance. I am willing to hit +2 on removing support for platforms that do not meet PCI compliance, specially when in the cases here, it is a matter of broken FSP blobs and not broken silicon per-se.
Also, I should not be accepting new callers for dev_find_slot() due the ill semantics it has. Prior to device enumeration, it can return false positives because all devices appear on bus 0. So please look for alternative solution if you want to support Intel's initiative of more blob less FOSS.
I perfectly understand your concerns, hence the sarcastic commit message. This patch is meant to be a "less bad" CB:35087 variant, as it allows printing where errors happen.
If this patch were to be merged in as-is, it would mean the platforms it affects would now be deprecated and marked for removal unless platforms don't cause any BUGs to appear in logs (so this patch shouldn't be necessary for them anyway).
Unfortunately, I do not have any hardware for many of these platforms, so I cannot fix coreboot for them. To clean up the blob mess in here in a reasonable timeframe, one would have to perform more than a dozen tests per hour. Help is appreciated.