[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Subrata Banik (Code Review)]

Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Aamir Bohra, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35026

to look at the new patch set (#6).

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
......................................................................

soc/intel/{cnl, icl}: Cache the TSEG region

This patch helps to save additional ~15ms of booting time in
normal boot and s3 resume on CML-hatch.

BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot

Without this CL:
Total Time: 929ms

With this CL: (TSEG marked as WB)
Total Time: 910ms

For test marked TSEG as WP/WC:
Total Time: ~920ms

Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/icelake/memmap.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35026/6