[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE

[Jon Murphy (Code Review)]

Jon Murphy has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83680?usp=email )

Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
......................................................................

soc/intel/adl: Update DCACHE_BSP_STACK_SIZE

During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.

BUG=None
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner 
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 470dbf4..632798e 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -191,12 +191,12 @@

config DCACHE_BSP_STACK_SIZE
    hex
-	default 0x80400
+	default 0x88000
    help
      The amount of anticipated stack usage in CAR by bootblock and
      other stages. In the case of FSP_USES_CB_STACK default value will be
      sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
-	  (~1KiB).
+	  (~32KiB).

config FSP_TEMP_RAM_SIZE
    hex