Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Subrata Banik, Patrick Rudolph, Venkata Krishna Nimmagadda, Caveh Jalali, Roy Mingi Park, Tim Wawrzynczak, Puthikorn Voravootivat, Nick Vaccaro, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39346
to look at the new patch set (#9).
Change subject: soc/intel/tigerlake: Add processor power limits control support ......................................................................
soc/intel/tigerlake: Add processor power limits control support
Add processor power limits control support to under soc/intel/common code. Also, configure these processor power limit controls for tigerlake platform.
BRANCH=None BUG=b:149722146 TEST=Built and checked this entry on Volteer system, cat /sys/class/powercap/intel-rapl/intel-rapl:0/*
CQ-DEPEND=CB:39345 Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/common/Makefile.inc A src/soc/intel/common/power_limit.c A src/soc/intel/common/power_limit.h A src/soc/intel/tigerlake/acpi/dptf.asl M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/include/soc/msr.h M src/soc/intel/tigerlake/systemagent.c 9 files changed, 313 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39346/9