Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47450 )
Change subject: soc/intel/denverton_ns: Hook up SMMSTORE ......................................................................
soc/intel/denverton_ns: Hook up SMMSTORE
UNTESTED.
Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47450/1
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..cae8b9b 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -10,6 +10,7 @@ #include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> +#include <smmstore.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -197,6 +198,26 @@ fast_spi_init(); }
+static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -245,6 +266,10 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; }
mainboard_smi_apmc(reg8);