[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage

[Subrata Banik (Code Review)]

Hello Raj Astekar, Patrick Rudolph, Aaron Durbin, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36552

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
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soc/intel/tigerlake/romstage: Do initial SoC commit till romstage

Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
   5.a Clean up upd override in fsp_params.c,
    will be added once FSP available.
   5.b Remove __weak functions from fsp_params.c
6. Add CPU/PCH/SA EDS document number and chapter number
7. Add required headers into include/soc/ from ICL directory

Tiger Lake specific changes will follow in subsequent patches.
1. FSP-M related UPD overrides

"The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.

The patch has been tested on real hardware."

Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87
Signed-off-by: Subrata Banik 
---
A src/soc/intel/tigerlake/include/soc/romstage.h
A src/soc/intel/tigerlake/include/soc/soc_chip.h
A src/soc/intel/tigerlake/include/soc/systemagent.h
A src/soc/intel/tigerlake/romstage/Makefile.inc
A src/soc/intel/tigerlake/romstage/fsp_params.c
A src/soc/intel/tigerlake/romstage/pch.c
A src/soc/intel/tigerlake/romstage/romstage.c
A src/soc/intel/tigerlake/romstage/systemagent.c
8 files changed, 402 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/5