[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40794 )

Change subject: sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register
......................................................................

sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/usb_ehci.c
4 files changed, 4 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/40794/1

diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index e5b7906..434d0aa 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -247,8 +247,7 @@
    pci_write_config32(dev, 0x120, reg32);

/* Set Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);

reg8 = pci_read_config8(dev, 0x4d); // Docking Status
    reg8 &= ~(1 << 7); // Docking not supported
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index f26d584..b76116d 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -13,12 +13,8 @@

static void i82801ix_enable_device(struct device *dev)
 {
-	u32 reg32;
-
    /* Enable SERR */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 }

static void i82801ix_early_settings(const config_t *const info)
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index d170f0d..5471e69 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -20,9 +20,7 @@
    printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");

/* Enable Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);

/* Set Cache Line Size to 0x10 */
    // This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index 3ccffd8..9759186 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -11,12 +11,8 @@

static void usb_ehci_init(struct device *dev)
 {
-	u32 reg32;
-
    printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);

printk(BIOS_DEBUG, "done.\n");
 }