[coreboot-gerrit] Change in coreboot[master]: /soc/intel:Update tcc offset for fleex

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/29351

Change subject: /soc/intel:Update tcc offset for fleex
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/soc/intel:Update tcc offset for fleex

Change tcc offset from 0 to 10.
Refer to b:117789732#comment20.

BUG=b:117789732
TEST=Match the result from TAT UI

Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su 
---
M src/soc/intel/apollolake/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29351/1

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index d2ec6c1..eeb0c12 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -198,6 +198,12 @@
    s3wake = pmc_fill_power_state(ps) == ACPI_S3;
    fsp_memory_init(s3wake);

+	/* Set TCC offset */
+	msr_t msr;
+	msr.lo = 0xa690000;
+	msr.hi = 0x0;
+	wrmsr(0x1a2, msr);
+
    if (punit_init())
    	set_max_freq();
    else