[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 )

Change subject: soc/mediatek: Add timestamp to measure PERST# time
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Patch Set 10:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62933/comment/ea1eb095_430926c3 
PS10, Line 7: Add timestamp to measure PERST# time
Ensure PERST# deassertion time follows the spec

https://review.coreboot.org/c/coreboot/+/62933/comment/985d5ec4_103870fd 
PS10, Line 9: Add timestamp support to measure the assertion time of PERST#.
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay.

File src/soc/mediatek/common/pcie.c:

https://review.coreboot.org/c/coreboot/+/62933/comment/dd072b45_3384db34 
PS3, Line 238: 	perst_time_us = mtk_pcie_perst_elapsed_time();
             : 	printk(BIOS_DEBUG, "%s: %lld us elapsed since assert PERST#\n",
             : 	       __func__, perst_time_us);
             : 
             : 	/*
             : 	 * Described in PCIe CEM specification sections 2.2
             : 	 * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)).
             : 	 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
             : 	 * for the power and clock to become stable.
             : 	 */
             : 	if (perst_time_us < 100000)
             : 		printk(BIOS_WARNING, "%s: PERST# assert time %lld us may not enough for link up\n",
             : 		       __func__, perst_time_us);
             :
> Is that ok to use udelay()?

Fine.

File src/soc/mediatek/common/pcie.c:

https://review.coreboot.org/c/coreboot/+/62933/comment/3eb1f98d_d894159c 
PS10, Line 249: 		mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true);
We should mdelay(100) in this case (and print a warning).

https://review.coreboot.org/c/coreboot/+/62933/comment/d99e9d8f_4f03a786 
PS10, Line 251: 100000
Add a local variable (maybe right above line#248)

const uint64_t min_perst_time_us = 100000;  /* 100 ms */