Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46821 )
Change subject: cpu/x86/mpinit/sipi_vector: Move code to C ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46821/1/src/cpu/x86/sipi_vector_c_h... File src/cpu/x86/sipi_vector_c_handler.c:
https://review.coreboot.org/c/coreboot/+/46821/1/src/cpu/x86/sipi_vector_c_h... PS1, Line 70: Enable Disable
https://review.coreboot.org/c/coreboot/+/46821/4/src/cpu/x86/sipi_vector_c_h... File src/cpu/x86/sipi_vector_c_handler.c:
https://review.coreboot.org/c/coreboot/+/46821/4/src/cpu/x86/sipi_vector_c_h... PS4, Line 40: intel_microcode_load_unlocked The update trigger mechanism is the same for AMD CPUs (wrmsr 0x79), maybe that can be placed in a more generic place as this seems to do more Intel specific things?
https://review.coreboot.org/c/coreboot/+/46821/4/src/cpu/x86/sipi_vector_c_h... PS4, Line 70: Enable Disable
https://review.coreboot.org/c/coreboot/+/46821/4/src/include/cpu/x86/mp.h File src/include/cpu/x86/mp.h:
https://review.coreboot.org/c/coreboot/+/46821/4/src/include/cpu/x86/mp.h@16... PS4, Line 162: /* This also needs to match the assembly code for saved MSR encoding. */ stale comment.