Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 )
Change subject: arch/x86/postcar: Configure MMU along with MTRRs ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93 PS3, Line 93: */ Ok.. I get the connection of PTE and MTRR now. I think you could just say that anything memory is WRBACK, from 0..TOLM and 4GiB..TOM. With MTRRs that cannot be easily done because of register alignment restrictions.
Also the exact MTRR programming you see here gets discarded during ramstage. Anything WRBACK probably stays WRBACK, but some UC could (or should) be adjusted to WRCOMB after PCI enumeration.
We might not currently make that WRCOMB setting, but any PCI MMIO with write-prefetch flag could gain some performance if we did. The UC tags from pagetables set here would void that.