Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
soc/intel/baytrail/sata.c: Fix SATA init sequence
SeaBIOS on Bay Trail would time out when trying to access a SATA drive. Turns out that there's two mistakes in the SATA initialization sequence:
- PCI register 0x94 is wrongly cleared with a bitwise-and operation. - PCI register 0x9c is instead written to 0x98, clobbering the latter.
After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.
Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Máté Kukri kukri.mate@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/sata.c 1 file changed, 2 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Máté Kukri: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea4..24c805a 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -128,14 +128,12 @@
/* Enable clock for ports */ reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; + reg32 &= ~(config->sata_port_map << 24); pci_write_config32(dev, 0x94, reg32);
/* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + pci_write_config32(dev, 0x9c, reg32); }
static void sata_enable(struct device *dev)