Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34657 )
Change subject: Documentation/soc/intel: Add documentation for MCU update ......................................................................
Patch Set 14: Code-Review-1
(12 comments)
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... File Documentation/soc/intel/ucode_update/microcode_update_model.md:
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 1: Microcode update mechanism for devices in field #
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 5: Processor microcode (MCU) is akin to processor firmware. Processors may remove whitespace on all lines
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 6: need updates to their microcode to operate correctly. These updates fix whitespace
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 10: ##Problem Statement what about other microcode update mechanisms? Why isn't it sufficient to update in bootblock?
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 13: by vboot (chrome root of trust - CROT) before it is allowed to run on whitespace
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 17: proposal tries to address the issue period
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 19: Prior to CPU reset, the CPU HW locates the FIT table from the storage, FIT specific. move to FIT documentation.
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 37: 1. Top swap, which enables the BIOS to have 2 bootblocks and bot from boot
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 41: The idea is to have 2 bootblocks, each having its own FIT table. The FIT mention downsides
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 57: a. bb_ro_ucode contains a FIT which has pointer to MCU invalid identation
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 64: a. Reserve a region in the FMAP which is equal to or greater invalid identation
https://review.coreboot.org/c/coreboot/+/34657/14/Documentation/soc/intel/uc... PS14, Line 73: **Flash Layout** not shown