Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52258 )
Change subject: soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC ......................................................................
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC
TEST=boot from SPI-NOR and show console message at bootblock stage.
Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8195/Kconfig A src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/bootblock.c A src/soc/mediatek/mt8195/emi.c A src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/emi.h A src/soc/mediatek/mt8195/include/soc/memlayout.ld A src/soc/mediatek/mt8195/include/soc/pll.h A src/soc/mediatek/mt8195/include/soc/spi.h A src/soc/mediatek/mt8195/soc.c A src/soc/mediatek/mt8195/spi.c 11 files changed, 302 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/52258/1
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig new file mode 100644 index 0000000..090ca2f --- /dev/null +++ b/src/soc/mediatek/mt8195/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8195 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8195 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc new file mode 100644 index 0000000..ab7561f --- /dev/null +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -0,0 +1,31 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) + +bootblock-y += bootblock.c +bootblock-y += ../common/mmu_operations.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-y += ../common/timer.c +bootblock-y += ../common/uart.c + +verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-y += ../common/timer.c +verstage-y += ../common/uart.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c +romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-y += ../common/timer.c +romstage-y += ../common/uart.c + +ramstage-y += emi.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-y += soc.c +ramstage-y += ../common/timer.c +ramstage-y += ../common/uart.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c new file mode 100644 index 0000000..f48e78c --- /dev/null +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} diff --git a/src/soc/mediatek/mt8195/emi.c b/src/soc/mediatek/mt8195/emi.c new file mode 100644 index 0000000..120665a --- /dev/null +++ b/src/soc/mediatek/mt8195/emi.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h new file mode 100644 index 0000000..0f4bb8b --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PMIF_SPI_BASE = IO_PHYS + 0x00024000, + PMICSPI_MST_BASE = IO_PHYS + 0x00025000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, + DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + DEVAPC_PERI_AO_BASE = IO_PHYS + 0x00034000, + DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, + DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, + DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, + EMI0_BASE = IO_PHYS + 0x00219000, + EMI1_BASE = IO_PHYS + 0x0021D000, + I2C_DMA_BASE = IO_PHYS + 0x00220080, + EMI1_SUB_BASE = IO_PHYS + 0x00225000, + EMI0_MPU_BASE = IO_PHYS + 0x00226000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, + DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, + DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, + DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, + AUXADC_BASE = IO_PHYS + 0x01001000, + UART0_BASE = IO_PHYS + 0x01001100, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01018000, + SPI5_BASE = IO_PHYS + 0x01019000, + SPIS0_BASE = IO_PHYS + 0x0101D000, + SPIS1_BASE = IO_PHYS + 0x0101E000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + MSDC0_BASE = IO_PHYS + 0x01230000, + SFLASH_REG_BASE = IO_PHYS + 0x0132C000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, + MIPITX_BASE = IO_PHYS + 0x01C80000, + IOCFG_BM_BASE = IO_PHYS + 0x01D10000, + IOCFG_BL_BASE = IO_PHYS + 0x01D30000, + IOCFG_BR_BASE = IO_PHYS + 0x01D40000, + I2C_BASE = IO_PHYS + 0x01E00000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, + IOCFG_TL_BASE = IO_PHYS + 0x01F40000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + UFSHCI_BASE = IO_PHYS + 0x01FA0000, + DISP_OVL0_BASE = IO_PHYS + 0x0C000000, + DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, + DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, + DISP_CCORR0_BASE = IO_PHYS + 0x0C004000, + DISP_AAL0_BASE = IO_PHYS + 0x0C005000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, + DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, + DSI0_BASE = IO_PHYS + 0x0C008000, + DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, + DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, + SMI_LARB0 = IO_PHYS + 0x0C018000, + VDOSYS0_BASE = IO_PHYS + 0x0C01A000, + SMI_BASE = IO_PHYS + 0x0C01B000, +}; +#endif diff --git a/src/soc/mediatek/mt8195/include/soc/emi.h b/src/soc/mediatek/mt8195/include/soc/emi.h new file mode 100644 index 0000000..33ff1bf --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/emi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_EMI_H +#define SOC_MEDIATEK_MT8195_EMI_H + +#include <stddef.h> + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8195_EMI_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld new file mode 100644 index 0000000..5942776 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 64K) + +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + CBFS_MCACHE(0x00107c00, 8K) + TIMESTAMP(0x00109c00, 1K) + STACK(0x0010a000, 12K) + TTB(0x0010d000, 28K) + DMA_COHERENT(0x00114000, 4K) + /* + * MCUPM exchanges data with kernel driver using SRAM 0x00115000 ~ + * 0x0011ffff. The address is hardcoded in MCUPM image and is unlikely + * to change. + */ + REGION(mcufw_reserved, 0x00115000, 44K, 4K) + /* MT8195 has 192KB SRAM. */ + SRAM_END(0x00130000) + + /* + * The L3 (can be used as SRAM_L2C) is 2MB in total. However the BootROM + * has configured only half of L2/L3 cache as SRAM so we can't use them + * unless if we disable L2C and reconfigure. + */ + SRAM_L2C_START(0x00200000) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ + BOOTBLOCK(0x00201000, 60K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x00210000, 240K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) + PRERAM_CBFS_CACHE(0x00290000, 48K) + PRERAM_CBMEM_CONSOLE(0x0029c000, 400K) + SRAM_L2C_END(0x00300000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h new file mode 100644 index 0000000..b8a36fd --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_PLL_H +#define SOC_MEDIATEK_MT8195_PLL_H + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* SOC_MEDIATEK_MT8195_PLL_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h new file mode 100644 index 0000000..cfa4f43 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/spi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MTK_MT8195_SPI_H +#define MTK_MT8195_SPI_H + +#include <spi-generic.h> + +#endif diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c new file mode 100644 index 0000000..af28dd4 --- /dev/null +++ b/src/soc/mediatek/mt8195/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8195_ops = { + CHIP_NAME("SOC Mediatek MT8195") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c new file mode 100644 index 0000000..459e46a --- /dev/null +++ b/src/soc/mediatek/mt8195/spi.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/spi.h> + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);