[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 142: 	set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
I wonder how this works.
My tests on Sandy Bridge showed that MTRRs are only updated on CR0.CD=1 to CR0.CD=0 transitions. All of AMD and early Intel CPUs follow this scheme and update MTRRs with cache disabled.
Isn't that transition required any more starting with APL?
"Intel® 64 and IA-32 Architectures Software Developer’s Manual" doesn't mention that.