[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Decouple USB config from MRC

13 Mar 2021

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51440 )
Change subject: nb/intel/haswell: Decouple USB config from MRC
......................................................................
nb/intel/haswell: Decouple USB config from MRC
Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
M src/mainboard/asrock/b85m_pro4/romstage.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/slippy/variants/falco/romstage.c
M src/mainboard/google/slippy/variants/leon/romstage.c
M src/mainboard/google/slippy/variants/peppy/romstage.c
M src/mainboard/google/slippy/variants/wolf/romstage.c
M src/mainboard/hp/folio_9480m/romstage.c
M src/mainboard/intel/baskingridge/romstage.c
M src/mainboard/lenovo/t440p/romstage.c
M src/mainboard/msi/h81m-p33/romstage.c
M src/mainboard/supermicro/x10slm-f/romstage.c
M src/northbridge/intel/haswell/raminit.h
M src/northbridge/intel/haswell/romstage.c
14 files changed, 52 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/51440/1

diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 1c17fcb..eb62594 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -25,7 +25,7 @@
    spd_map[3] = 0xa6;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -43,7 +43,7 @@
    { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    { 1, 0 },
    { 1, 0 },
    { 1, 1 },
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 16b1500..162b877 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -23,7 +23,7 @@
    spd_map[2] = 0xa4;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,7 +41,7 @@
    { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0 },
    { 1, 0 },
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index dda2edc..f8a5959 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -46,7 +46,7 @@
    spd_map[2] = 0xa4;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0064, 1, 0,               /* P0: VP8 */
      USB_PORT_MINI_PCIE },
@@ -66,7 +66,7 @@
      USB_PORT_SKIP },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0 }, /* P1; CN22 */
    { 1, 1 }, /* P2; CN23  */
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 21a4ec6..e688760 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -25,7 +25,7 @@
    }
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0064, 1, 0,               /* P0: Port A, CN8 */
      USB_PORT_BACK_PANEL },
@@ -45,7 +45,7 @@
      USB_PORT_INTERNAL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0               }, /* P1; Port A, CN8 */
    { 1, 0               }, /* P2; Port B, CN9  */
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index 938590b..7ab867f 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -22,7 +22,7 @@
    	memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN);
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0,               /* P0: Port A, CN10 */
      USB_PORT_BACK_PANEL },
@@ -42,7 +42,7 @@
      USB_PORT_SKIP },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0               }, /* P1; Port A, CN10 */
    { 1, 2               }, /* P2; Port B, CN11 */
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 02b47db..bfb24f1 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -39,7 +39,7 @@
    }
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
      USB_PORT_MINI_PCIE },
@@ -59,7 +59,7 @@
      USB_PORT_SKIP },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0               }, /* P1; Port A, CN6 */
    { 0, USB_OC_PIN_SKIP }, /* P2; */
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 939d584..8d8df94 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -25,7 +25,7 @@
    }
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0,               /* P0: Port A, CN10 */
      USB_PORT_BACK_PANEL },
@@ -45,7 +45,7 @@
      USB_PORT_SKIP  },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0               }, /* P1; Port A, CN10 */
    { 1, 2               }, /* P2; Port B, CN11  */
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
index 496005d..ffef6d2 100644
--- a/src/mainboard/hp/folio_9480m/romstage.c
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -23,7 +23,7 @@
    spd_map[2] = 0xa4;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
    { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
@@ -35,7 +35,7 @@
    { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    { 1, USB_OC_PIN_SKIP }, /* dock */
    { 1, USB_OC_PIN_SKIP }, /* left */
    { 1, USB_OC_PIN_SKIP }, /* right */
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index dc1f50f..7e09ab1 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -49,7 +49,7 @@
    spd_map[3] = 0xa6;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, /* P0: Back USB3 port  (OC0) */
      USB_PORT_BACK_PANEL },
@@ -81,7 +81,7 @@
      USB_PORT_FRONT_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 0 }, /* P1; */
    { 1, 0 }, /* P2; */
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 7aca7c5..fd11d15 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -46,7 +46,7 @@
    spd_map[2] = 0xa2;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
@@ -64,7 +64,7 @@
    { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    { 1, 0 },
    { 1, 0 },
    { 1, USB_OC_PIN_SKIP },
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c
index 9bcb400..df7de43 100644
--- a/src/mainboard/msi/h81m-p33/romstage.c
+++ b/src/mainboard/msi/h81m-p33/romstage.c
@@ -23,7 +23,7 @@
    spd_map[2] = 0xa4;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,7 +41,7 @@
    { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    { 1, 0 },
    { 1, 0 },
    { 1, 1 },
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 36f79a3..e52dbb3 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -25,7 +25,7 @@
    spd_map[3] = 0xa6;
 }
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS] = {
    /* Length, Enable, OCn#, Location */
    { 0x0040, 1, 0, USB_PORT_INTERNAL },
    { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -43,7 +43,7 @@
    { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
 };
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS] = {
    /* Enable, OCn# */
    { 1, 1 },
    { 1, 1 },
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 6efea3e..5cf4566 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -6,9 +6,24 @@
 #include <stdint.h>
 #include "pei_data.h"
+#define NUM_USB2_PORTS	14
+#define NUM_USB3_PORTS	6
+
+struct usb2_port_config {
+	uint16_t length;
+	uint8_t enable;
+	uint8_t oc_pin;
+	uint8_t location;
+} __packed;
+
+struct usb3_port_config {
+	uint8_t enable;
+	uint8_t oc_pin;
+} __packed;
+
 /* Mainboard-specific USB configuration */
-extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
-extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
+extern const struct usb2_port_config mainboard_usb2_ports[NUM_USB2_PORTS];
+extern const struct usb3_port_config mainboard_usb3_ports[NUM_USB3_PORTS];
/* Optional function to copy SPD data for on-board memory */
 void copy_spd(struct pei_data *peid);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 48ba476..ae51558 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -71,8 +71,17 @@
    	.usb_xhci_on_resume	= cfg->usb_xhci_on_resume,
    };
-	memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports));
-	memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports));
+	for (size_t i = 0; i < NUM_USB2_PORTS; i++) {
+		pei_data.usb2_ports[i].length		= mainboard_usb2_ports[i].length;
+		pei_data.usb2_ports[i].enable		= mainboard_usb2_ports[i].enable;
+		pei_data.usb2_ports[i].over_current_pin	= mainboard_usb2_ports[i].oc_pin;
+		pei_data.usb2_ports[i].location		= mainboard_usb2_ports[i].location;
+	}
+
+	for (size_t i = 0; i < NUM_USB3_PORTS; i++) {
+		pei_data.usb3_ports[i].enable		= mainboard_usb3_ports[i].enable;
+		pei_data.usb3_ports[i].over_current_pin	= mainboard_usb3_ports[i].oc_pin;
+	}
enable_lapic();
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/51440
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Gerrit-Change-Number: 51440
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-MessageType: newchange



    

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[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Decouple USB config from MRC