Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34988 )
Change subject: mediatek/mt8183: Implement the dramc init setting ......................................................................
Patch Set 17:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... PS9, Line 679: u8 MR01Value[FSP_MAX] = {0x26, 0x56}; : u8 MR13Value = (1 << 4) | (1 << 3);
MR01Value and MR13Value will used at other function for dynamic adjust some settings. […]
Done
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... PS9, Line 1343: : if (freq_group == LP4X_DDR1600) : dramc_setting_DDR1600(); : else if (freq_group == LP4X_DDR2400) : dramc_setting_DDR2400(); : else if (freq_group == LP4X_DDR3600) : dramc_setting_DDR3600();
the default setting is designed for 3200 case, for other frequency need more settings to overwrite d […]
Done
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... PS9, Line 1576: u8 dqsinctl, datlat, new_datlat, trcd, trrd, twr, twtr, trc, tras; : u8 trp, trpab, tfaw, trtw_ODT_on, trtp, txp, refcnt; : u8 trfc, trfcpb, tzqcs, refcnt_fr_clk, txrefcnt, tmrr2w_ODT_on; : u8 twtpd, trtpd, xrtw2w, xrtw2r, xrtr2w, xrtr2r, twtr_05T; : u8 trtw_ODT_on_05T, twtpd_05T, trtpd_05T, tfaw_05T, trrd_05T; : u8 twr_05T, tras_05T, trpab_05T, trp_05T, trcd_05T, trtp_05T; : u8 txp_05T, trfc_05T, trfcpb_05T, trc_05T, r_dmcatrain_intv; : u8 r_dmmrw_intv, r_dmfspchg_prdcnt, ckeprd, ckelckcnt, zqlat2;
Done
Done