[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Expose UPD to disable Precision Time Measurement

[Duncan Laurie (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46856

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Expose UPD to disable Precision Time Measurement
......................................................................

soc/intel/tigerlake: Expose UPD to disable Precision Time Measurement

Expose a config option that allows disabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port.  Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.

BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46856/2