[coreboot-gerrit] Change in coreboot[master]: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44880 )

Change subject: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]
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Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44880/15/src/security/intel/txt/get... 
File src/security/intel/txt/getsec_enteraccs.S:

https://review.coreboot.org/c/coreboot/+/44880/15/src/security/intel/txt/get... 
PS15, Line 111: Disable all MTRRs
> FYI that on DeltaLake, coreboot sets default memory attribute as WB instead of UC, through MSR 0x2ff […]

MSR 0x2ff is MTRR_DEF_TYPE_MSR, so yes, this can cause problems. This has been handled in CB:46375 though.