Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41024
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support
Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
Include TCSS TBT PCIE Root Port 0/1/2/3 inside _SB.PCIx (where x depends on PCI multiple segment support).
Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 85 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/3