[coreboot-gerrit] Change in ...coreboot[master]: mb/pcengines/apu1/romstage.c: Add possibility to redirect output to COM2

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29791

Change subject: mb/pcengines/apu1/romstage.c: Add possibility to redirect output to COM2
......................................................................

mb/pcengines/apu1/romstage.c: Add possibility to redirect output to COM2

Enable COM2 port on SuperIO if UART index is 1. This change allows
to use full RS232 COM1 port for different purposes when COM2 is selected
as main port.

Signed-off-by: Michał Żygowski 
Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4
---
M src/mainboard/pcengines/apu1/romstage.c
1 file changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29791/1

diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index ab48943..fb56e8e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -21,9 +21,11 @@
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
 #include <SB800.h>
+#include <build.h>

#define SIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)

static void early_lpc_init(void)
 {
@@ -60,6 +62,18 @@

void board_BeforeAgesa(struct sysinfo *cb)
 {
+	pci_devfn_t dev;
+	u32 data;
+
    early_lpc_init();
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	dev = PCI_DEV(0, 0x14, 3);
+	data = pci_read_config32(dev, 0x48);
+	/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
+	pci_write_config32(dev, 0x48, data | 3);
+
+	if (CONFIG_UART_FOR_CONSOLE == 1)
+		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+	else if (CONFIG_UART_FOR_CONSOLE == 0)
+		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
 }