[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Ravindra, Subrata Banik, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )

Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
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Patch Set 12:

(1 comment)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/55364/comment/309bcca3_93dc0868 
PS12, Line 140:
> Ack

Looks like list of timestamp ids(940-950: Intel ME) assigned for ME are fully utilized. I need to take new range(600-650) for ME in addition to 940-950 range. Is that ok?