Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74379 )
Change subject: mb/google/rex/baseboard/rex: Add cpu power limits ......................................................................
mb/google/rex/baseboard/rex: Add cpu power limits
Add CPU power limits support and values for Meteor Lake based rex board
BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values on Rex board
Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc A src/mainboard/google/rex/variants/baseboard/rex/ramstage.c M src/mainboard/google/rex/variants/rex0/Makefile.inc A src/mainboard/google/rex/variants/rex0/ramstage.c 6 files changed, 109 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/74379/1
diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index c1c22db..7d5f01d 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -30,6 +30,12 @@ fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ }
void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index b51517c..bc107bd 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -29,4 +29,20 @@
void variant_generate_s0ix_hook(enum s0ix_entry entry);
+/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(const struct cpu_power_limits *limits, + size_t num_entries); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc index fd45b94..bb3620a 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc +++ b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc @@ -1 +1,3 @@ romstage-y += memory.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c new file mode 100644 index 0000000..ed636aa --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> + +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +WEAK_DEV_PTR(dptf_policy); + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4(W) (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); + } + } +} diff --git a/src/mainboard/google/rex/variants/rex0/Makefile.inc b/src/mainboard/google/rex/variants/rex0/Makefile.inc index cdbf407..95a700a 100644 --- a/src/mainboard/google/rex/variants/rex0/Makefile.inc +++ b/src/mainboard/google/rex/variants/rex0/Makefile.inc @@ -2,4 +2,5 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/rex/variants/rex0/ramstage.c b/src/mainboard/google/rex/variants/rex0/ramstage.c new file mode 100644 index 0000000..7d37182 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* Following values are for performance config as per document #640982 */ + { PCI_DID_INTEL_MTL_P_ID_1, 45, 18000, 45000, 115000, 115000, 197000 }, + { PCI_DID_INTEL_MTL_P_ID_2, 15, 6000, 15000, 57000, 57000, 101000 }, + { PCI_DID_INTEL_MTL_P_ID_5, 15, 6000, 15000, 57000, 57000, 101000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +}