Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48346 )
Change subject: azalia: Make `set_bits` function non-static ......................................................................
azalia: Make `set_bits` function non-static
There's many copies of this function in the tree. Make the copy in azalia_device.c non-static and rename it to `azalia_set_bits`, then replace all other copies with it. Since azalia_device.c is only built when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.
This has the side-effect of building hda_verb.c from the mainboard directory. If this patch happens to break audio on a mainboard, it's because its hda_verb.c was always wrong but wasn't being compiled.
Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/soc/intel/common/Kconfig.common M src/soc/intel/common/hda_verb.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/hda_verb.c 16 files changed, 32 insertions(+), 213 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 4ab45bc..543d5cb 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -7,7 +7,7 @@ #include <device/mmio.h> #include <delay.h>
-static int set_bits(void *port, u32 mask, u32 val) +int azalia_set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -40,7 +40,7 @@ int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec;
/* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -62,11 +62,11 @@ goto no_codec;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ @@ -80,7 +80,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); return 0; } diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index d682772..7bb8e10 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -18,6 +18,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1)
+int azalia_set_bits(void *port, u32 mask, u32 val); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops;
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index ba0b2db..1a59d04 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON bool + select AZALIA_PLUGIN_SUPPORT select HAVE_DISPLAY_MTRRS help common code for Intel SOCs diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 83bbb59..57104c4 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -7,39 +7,12 @@
#include "hda_verb.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - int hda_codec_detect(u8 *base) { u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ @@ -51,11 +24,11 @@ write8(base + HDA_STATESTS_REG, 0xf);
/* Turn off the link and poll RESET# bit until it reads back as 0 */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) goto no_codec;
/* Turn on the link and poll RESET# bit until it reads back as 1 */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ @@ -69,7 +42,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); printk(BIOS_DEBUG, "HDA: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7852ace..3b05a3e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -11,6 +11,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 972b253..5e810c4 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -14,39 +14,12 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ @@ -63,7 +36,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 50f7c60..2d3bf24 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select IOAPIC select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 1927adc..a511468 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801gx.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 11a6d39..be640db 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index d6c7533..7078e67 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801ix.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 6abeac1..687cb45 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index bf41490..982efb7 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801jx.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07f9b6b..c54c7e4 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -8,6 +8,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select IOAPIC select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 97e705e2..0c19598 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -10,39 +10,12 @@ #include <device/azalia_device.h> #include "pch.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ @@ -59,7 +32,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ba86b8..a88a9a8 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -8,6 +8,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 24897ca..7c6537d 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -8,39 +8,12 @@ #include "pch.h" #include "hda_verb.h"
-static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - int hda_codec_detect(u8 *base) { u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ @@ -57,7 +30,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); printk(BIOS_DEBUG, "HDA: No codec!\n"); return 0; }