[coreboot-gerrit] [S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

[Yidi Lin (Code Review)]

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
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soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.

BUG=b:379008996
BRANCH=none
TEST=booted successfully

Signed-off-by: Vince Liu 
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Yidi Lin 
---
M src/soc/mediatek/mt8189/gpio.c
1 file changed, 37 insertions(+), 5 deletions(-)

Approvals:
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c
index 27179c3..dde8d14 100644
--- a/src/soc/mediatek/mt8189/gpio.c
+++ b/src/soc/mediatek/mt8189/gpio.c
@@ -8,6 +8,26 @@
 #include <device/mmio.h>
 #include <gpio.h>

+#define SPI_NOR_GPIO_BASE	150
+
+enum {
+	SPI_NOR_CK = 0,
+	SPI_NOR_CS = 1,
+	SPI_NOR_IO0 = 2,
+	SPI_NOR_IO1 = 3,
+	SPI_NOR_IO2 = 4,
+	SPI_NOR_IO3 = 5,
+};
+
+static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
+	[SPI_NOR_CK] = { 0x10, 12, 3, },
+	[SPI_NOR_CS] = { 0x10, 27, 3, },
+	[SPI_NOR_IO0] = { 0x10, 15, 3, },
+	[SPI_NOR_IO1] = { 0x10, 18, 3, },
+	[SPI_NOR_IO2] = { 0x10, 21, 3, },
+	[SPI_NOR_IO3] = { 0x10, 24, 3, },
+};
+
 static const struct gpio_drv_info gpio_driving_info[] = {
    [0] = { 0x10, 15, 3, },
    [1] = { 0x10, 9, 3, },
@@ -261,14 +281,26 @@

const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id)
 {
-	if (raw_id >= ARRAY_SIZE(gpio_driving_info))
-		return NULL;
-	return &gpio_driving_info[raw_id];
+	if (ENV_BOOTBLOCK) {
+		uint32_t id = raw_id - SPI_NOR_GPIO_BASE;
+
+		if (id >= ARRAY_SIZE(bootblock_gpio_driving_info))
+			return NULL;
+		return &bootblock_gpio_driving_info[id];
+	} else {
+		if (raw_id >= ARRAY_SIZE(gpio_driving_info))
+			return NULL;
+		return &gpio_driving_info[raw_id];
+	}
 }

const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id)
 {
-	if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
+	if (ENV_BOOTBLOCK) {
    	return NULL;
-	return &gpio_driving_adv_info[raw_id];
+	} else {
+		if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
+			return NULL;
+		return &gpio_driving_adv_info[raw_id];
+	}
 }