[coreboot-gerrit] Change in coreboot[master]: mb/supermicro/x11ssm-f: enable LTR for all root ports

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48367 )

Change subject: mb/supermicro/x11ssm-f: enable LTR for all root ports
......................................................................

mb/supermicro/x11ssm-f: enable LTR for all root ports

Follow vendor and enable LTR on all root ports to optimize for devices'
latency requirements and also optimize power management while preventing
failure due to wrongly guessing idle states, which happens without LTR.

Tested successfully. No errors show up in dmesg.

Signed-off-by: Michael Niewöhner 
Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index d7f1873..a03ecc5 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -52,22 +52,27 @@
    	end
    	device pci 1c.0 on	# PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
    		register "PcieRpEnable[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
    		smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
    	end
    	device pci 1c.4 on	# PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
    		register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
    		smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
    	end
    	device pci 1d.0 on	# PCH PCIe Port 9
    		register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
    		device pci 00.0 on end	# GbE 1
    	end
    	device pci 1d.1 on	# PCH PCIe Port 10
    		register "PcieRpEnable[9]" = "1"
+			register "PcieRpLtrEnable[9]" = "1"
    		device pci 00.1 on end	# GbE 2
    	end
    	device pci 1d.2 on	# PCH PCIe Port 11
    		register "PcieRpEnable[10]" = "1"
+			register "PcieRpLtrEnable[10]" = "1"
    		device pci 00.0 on	# Aspeed PCI Bridge
    			device pci 00.0 on end	# Aspeed 2400 VGA
    		end