Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78900?usp=email )
Change subject: [WIP] soc/amd/genoa: add I2C support ......................................................................
[WIP] soc/amd/genoa: add I2C support
Still need to find out which type of pad control register is used for I2C4 and I2C5.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/chip.h A src/soc/amd/genoa/i2c.c A src/soc/amd/genoa/include/soc/i2c.h M src/soc/amd/genoa/include/soc/iomap.h 6 files changed, 122 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/78900/1
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 2e80af4..887bed9 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -18,6 +18,9 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR @@ -39,6 +42,10 @@ string default "soc/amd/genoa/chipset.cb"
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 150 + config EARLY_RESERVED_DRAM_BASE hex default 0x7000000 diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 506f6cf..e185714 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -5,6 +5,7 @@ all-y += reset.c all-y += config.c all-y += gpio.c +all-y += i2c.c all-y += uart.c
bootblock-y += early_fch.c diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h index 9168586..5713a72 100644 --- a/src/soc/amd/genoa/chip.h +++ b/src/soc/amd/genoa/chip.h @@ -4,9 +4,17 @@ #define __GENOA_CHIP_H__
#include <amdblocks/chip.h> +#include <amdblocks/i2c.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/iomap.h> +#include <types.h>
struct soc_amd_genoa_config { struct soc_amd_common_config common_config; + + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; };
#endif diff --git a/src/soc/amd/genoa/i2c.c b/src/soc/amd/genoa/i2c.c new file mode 100644 index 0000000..8052cfc --- /dev/null +++ b/src/soc/amd/genoa/i2c.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <soc/i2c.h> +#include <soc/southbridge.h> +#include "chip.h" + +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), + I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL), + I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL), +}; + +static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }, + { I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" }, + { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" } +}; + +void reset_i2c_peripherals(void) +{ + const struct soc_amd_genoa_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + const struct soc_amd_genoa_config *config = config_of_soc(); + + if (bus >= ARRAY_SIZE(config->i2c_pad)) + return; + + /* The I/O pads of I2C0..3 are the new I23C pads and the I/O pads of I2C3 still are the + same I2C pads as in Picasso and Cezanne. TODO: verify if this is true */ + if (bus <= 3) + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + else + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); +} + +const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); + return i2c_ctrlr; +} + +const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) +{ + const struct soc_amd_genoa_config *config = config_of_soc(); + + *num_buses = ARRAY_SIZE(config->i2c); + return config->i2c; +} diff --git a/src/soc/amd/genoa/include/soc/i2c.h b/src/soc/amd/genoa/include/soc/i2c.h new file mode 100644 index 0000000..ffff754 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/i2c.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_I2C_H +#define AMD_GENOA_I2C_H + +#include <gpio.h> +#include <types.h> + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C4_SCL BIT(4) +#define GPIO_I2C5_SCL BIT(5) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL | \ + GPIO_I2C4_SCL | GPIO_I2C5_SCL) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_149 +#define I2C3_SCL_PIN GPIO_151 +#define I2C4_SCL_PIN GPIO_13 +#define I2C5_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_149_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_151_IOMUX_GPIOxx +#define I2C4_SCL_PIN_IOMUX_GPIOxx GPIO_13_IOMUX_GPIOxx +#define I2C5_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void reset_i2c_peripherals(void); + +#endif /* AMD_GENOA_I2C_H */ diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h index 5b767e3..0e24780 100644 --- a/src/soc/amd/genoa/include/soc/iomap.h +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -3,6 +3,10 @@ #ifndef AMD_GENOA_IOMAP_H #define AMD_GENOA_IOMAP_H
+#define I2C_MASTER_DEV_COUNT 6 +#define I2C_PERIPHERAL_DEV_COUNT 0 +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + #define SPI_BASE_ADDRESS 0xfec10000
/* @Todo : Check these values for Genoa */