jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
There are some extra data transfer in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calc by video timing.
So dsi driver reduces the hbp and hfp to keep the line time.
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c 1 file changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/1
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb..66bc6b6 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -73,30 +73,28 @@
static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) { - u32 cycle_time, ui; - - ui = 1000 / data_rate + 0x01; - cycle_time = 8000 / data_rate + 0x01; + u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
memset(phy_timing, 0, sizeof(*phy_timing));
- phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); + phy_timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; + phy_timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; + phy_timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 - + phy_timing->da_hs_prepare + 1; + phy_timing->da_hs_trail = phy_timing->da_hs_prepare + 1;
- phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; + phy_timing->ta_go = 4 * phy_timing->lpx - 2; + phy_timing->ta_sure = phy_timing->lpx + 2; + phy_timing->ta_get = 4 * phy_timing->lpx; + phy_timing->da_hs_exit = 2 * phy_timing->lpx + 1;
phy_timing->da_hs_sync = 1; - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + phy_timing->clk_hs_zero = phy_timing->clk_hs_trail * 4; + phy_timing->clk_hs_trail = phy_timing->clk_hs_prepare;
- phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + phy_timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); + phy_timing->clk_hs_post = phy_timing->clk_hs_prepare + 8; + phy_timing->clk_hs_exit = 2 * phy_timing->clk_hs_trail;
/* Allow board-specific tuning. */ mtk_dsi_override_phy_timing(phy_timing); @@ -200,12 +198,12 @@ hspw = edid->mode.hspw;
hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) - * bytes_per_pixel - 10; + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel;
data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
u32 delta = 12; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) @@ -214,11 +212,13 @@ u32 d_phy = phy_timing->d_phy; if (d_phy == 0) d_phy = data_phy_cycles * lanes + delta; - if (hfp_byte > d_phy) - hfp_byte -= d_phy; - else + if ((hfp_byte + hbp_byte) > d_phy) { + hfp_byte -= (d_phy * hfp_byte) / (hfp_byte + hbp_byte); + hbp_byte -= (d_phy * hbp_byte) / (hfp_byte + hbp_byte); + } else { printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " "and the panel may not work properly.\n"); + }
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte);